The present specification relates generally to fabrication processes for integrated circuits (ICs). More specifically, the present specification relates to a photolithographic process for fabricating ICs.
The semiconductor industry has a need to manufacture integrated circuits (ICs) with higher and higher densities of devices on a smaller chip area to achieve greater functionality and to reduce manuacturing costs. This desire for large-scale integration has led to a continued shrinking of the circuit dimensions and features of the devices.
The ability to reduce the sizes of structures, such as gates in field effect transistors (FETs), is driven by lithographic technology which is, in turn, dependent upon the wavelength of light used to expose the photoresist. In current commercial fabrication processes, optical devices expose the photoresist using light having a wavelength of 248 nm (nanometers). Research and development laboratories are experimenting with the 193 nm wavelength to reduce the size of structures. Further, advanced lithographic technologies are being developed that utilize radiation having a wavelength of 157 nm and even shorter wavelengths, such as those used in Extreme Ultra-Violet (EUV) lithography (e.g., 13 nm).
One challenge facing lithographic technology is fabricating features having a critical dimension (CD) below 100 nm. All steps of the photolithographic techniques currently employed must be improved to achieve the further reduction in feature size. One step which must be improved is the patterning of photoresist (e.g., exposure and development) on the substrate.
In a conventional technique, a photoresist layer on a layer of material is exposed to light or radiation through a binary mask. The photoresist layer may be either a positive or a negative photoresist. The light causes a photochemical reaction in the photoresist. The photoresist is removable with a developer solution at the portions of the photoresist that are exposed through the mask. The photoresist is developed to clear away these portions, whereby a photoresist pattern of features remains on the layer of material. An integrated circuit feature, such as a gate, via, or interconnect, is then etched into the layer of material, and the remaining photoresist is removed.
The linewidth of the integrated circuit feature is limited using the conventional process by, for example, aberrations, focus, and proximity effects in the use of light. Using a 248 nm wavelength light source, the minimum printed feature linewidth is between 300 and 150 nm, using conventional techniques.
Photoresist is typically applied with a thickness of several thousands of Angstroms, in order to adequately resist the etchant during the etching step. However, a very thick photoresist layer can reduce the depth of focus or resolution of the photolithograhpic process. Thus, ultra-thin resists have been implemented. However, corner rounding problems and insufficient etch protection are associated with using thinner photoresists. The result is poor resolution.
Accordingly, there is a need for a method of reducing the linewidth of features fabricated in an integrated circuit. Further, there is a need for photoresist layer which has the benefits of a thin photoresist layer during exposure and the advantages of a thick photoresist layer during etching. Further still, there is a need for such a method which is simple and cost-effective to implement. The teachings hereinbelow extend to those embodiments which fall within the scope of the appended claims, regardless of whether they accomplish one or more of the above-mentioned needs.
According to an exemplary embodiment, a method of fabricating a feature of an integrated circuit in a layer of material includes providing a layer of photoresist having a first thickness over the layer of material. The method further includes forming apertures in the layer of photoresist and growing the layer of photoresist to a second thickness greater than the first thickness. The method further includes etching the layer of material through the apertures to fabricate a feature.
According to another exemplary embodiment, a method of fabricating a feature of an integrated circuit in a layer of material includes providing a self-assembled molecular structure having a first thickness over the layer of material. The method further includes forming apertures in the self-assembled molecular structure and growing the self-assembled molecular structure to a second thickness greater than the first thickness. The method further includes etching the layer of material through the apertures to fabricate a feature.
According to yet another exemplary embodiment, an integrated circuit has a feature, such as a transistor. The feature is fabricated by the process of providing a first layer of photoresist over the layer of material and forming apertures in the first layer of photoresist. The method further includes exposing the first layer of photoresist to a solution containing molecules capable of forming a self-assembled monolayer. The self-assembled molecule forms a second layer of photoresist over the first layer of photoresist. The process further includes etching the layer of material through the apertures to fabricate a feature.